CVE-2026-90124

/// Technical description

In the Linux kernel, the following vulnerability has been resolved:

irqchip/renesas-rzg2l: Fix loss of interrupt

rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a

read-modify-write on the ISCR/TSCR status registers to clear the bit

for the interrupt just handled. Since these registers are

write-0-to-clear per bit, this is racy:

If another interrupt's status bit gets set between the read and the write,

that bit is written back as 0 by the software-constructed value, clearing

an interrupt that hasn't been serviced yet and losing it.

This can be reproduced by triggering multiple interrupts at once, e.g.:

gpioset -c gpiochip0 355=0 353=0 328=0 352=0

Fix this by writing back only the bit being cleared, with all other bits

set to 1, instead of read-modify-writing the whole register. Since 1-bits

are left unchanged by hardware, concurrently-set status bits for other

interrupts are preserved.

/// Remediation

Check the references section for vendor advisories, patches, and mitigation guidance. If immediate patching is not possible, review the CVSS vector to understand the attack surface and apply compensating controls such as network segmentation or access restrictions.

/// References